Bias circuits are widely employed in analog or mixed signal electronic circuitry to set operating conditions by establishing a predetermined voltage at a given node. Typically, maintaining a bias node at a desired voltage consumes power. Therefore, bias circuits are often disabled in low-power or power-down operating states. A bias circuit may also require a length of time to generate a steady state voltage at the bias node, and the length of time may be related to power consumption and noise filtering.
Conventional bias circuits exhibit a number of limitations. As low power operation of electronic circuits becomes increasingly important, the capability to enter the lowest power state whenever possible becomes essential. Conventionally, bringing the bias circuits back online is a major limitation of quickly returning to an operational power state. This is often due to the fact that, in order to minimize any possible noise injection, bias nodes are often heavily bypassed to a supply rail. Additionally, large current surges in the supply network will likely induce ringing, further complicating a power-up of the circuit.
Power is consumed maintaining a steady-state voltage on a node that is not equal to a supply rail. For example, if the power supply is 1.0V and the ground return is 0V, then at least some on-chip power is consumed in the process of generating a non-rail voltage, such as 0.5V. Therefore, in the lowest power consumption mode (a “power-down” mode), a non-rail voltage is not maintained, and all nodes may be either pulled up to 1.0V or down to 0V.
Generally, during power-up of a circuit, greater power is consumed to obtain a non-rail voltage in less time. For example, a circuit may be configured to obtain the desired non-rail voltage (“operating point”) in minimal time, but may also consume excessive power during normal operation and cause a supply collapse by requiring a large current surge during the power-up. Further, in order to keep noise immunity, additional bypass capacitance may be placed from a bias line to a supply rail, further slowing down the activation of the bias line. Thus, to conserve operating power and maintain integrity of the supply, typical circuits generating non-rail voltages exhibit a relatively slow power-on process.
Further, typical bias circuits exhibit substantial capacitance at the supply node. Due to the inductance of the supply line and on-chip capacitance to reduce noise between the supply rails, any change in current to the bias circuit will induce a ringing in the supply voltage. The “severity” of the ringing will be dependent upon the magnitude of the current change, the speed of the surge, the value of the inductance and effective capacitance, and other factors.
On-chip frequency to current (F2I) circuits represent a specific class of bias circuits that are typically used to generate a frequency related current for other circuits. In some instances, a digitized F2I circuit may utilize a switched-cap scheme to maintain and settle the operating point of the F2I with a delta-modulator-based control system. As with conventional F2Is, this sort of digitized F2I circuit is heavily bypassed for noise filtering, thereby exacerbating the maintenance power issue as well as the length of time required to reach steady state.